In integrated circuits, and particularly in micro-logic circuits, there is often the necessity of integrating therewith specific circuits capable of ensuring the resetting of all of the functional elements of the integrated circuit to a certain state whenever power is switched on. This resetting must occur independently of the manner in which the supply voltage is raised from ground potential to the nominal supply voltage level, in order to prevent the occurrence of undesired and uncontemplated integrated circuit element configurations, which may cause malfunctioning and possibly latching of the whole integrated circuit device.
Such circuits are called power-on reset circuits, and are commonly referred to by the acronym POR. POR circuits perform the aforementioned function. These circuits are capable of generating a resetting pulse of predetermined characteristics upon switching on of the integrated circuit (i.e. when power is provided by a supply voltage).
Generally, these POR circuits have an architecture which includes power dissapative static current paths between the potential voltage nodes and, although these static current paths normally have a relatively high impedance, the persistence of a nonnegligeable static power consumption is not, in many cases, compatible with design specifications of CMOS integrated circuit devices, which typically have a null static consumption Therefore, these POR circuits may not be usable with many CMOS integrated circuit devices.
In addition, these POR circuits may internally cause malfunctioning if accidentally stimulated by internal or external transient events, e.g. noise induced by the switching of output buffers and the like.